Method of fabricating silicon capacitive sensor

ABSTRACT

Manufacturing all-silicon force sensors, such as capacitive pressure sensors ( 100, 200 ) that have long term stability and good linear sensitivity, and can be built into of a pneumatic tire. The sensors include buried electrical feedthrough ( 112   b ) to provide an electrical connection into a sealed silicon cavity ( 108 ). The buried feedthrough consists of a conductor ( 112   b ) in a shallow groove ( 106 ) in a substrate ( 102 ), communicating between the sensing cavity ( 108 ) and an external contact area ( 110 ). The sensor designs also feature a method for forming a silicon-to-silicon fusion bond (SFB) wherein at least one of the two surfaces ( 152, 252 ) to be has a tough silicon surface unsuitable for good SFB joints because it was bonded heavily boron-doped by means of diffusion. The method of this invention includes preparing each doped surface ( 152, 252 ) for SFB by polishing the surface with a Chemical-Mechanical Polishing (CMP) process. The sensor designs can also include optional reference capacitors ( 141, 241 ) on the same chip ( 100, 200 ) as the sensing capacitor ( 140, 240 ). The reference capacitors ( 141, 241 ) are insensitive to pressure (force), but respond to ambient temperature changes in the same way as the sensing capacitor. Suitable external interface circuits can utilize the reference capacitors ( 141, 241 ) to pull out the majority of ambient temperature effects.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of commonly-owned, U.S. ProvisionalPatent Application No. 60/091,909, filed Jul. 7, 1998 by Ko et al.

Attention is directed to commonly-owned, copending PCT patentapplication Ser. No. PCT/US99/15270 entitled DUAL OUTPUT CAPACITANCEINTERFACE CIRCUIT filed on Jul. 7, 1999.

TECHNICAL FIELD OF THE INVENTION

The invention relates to pressure sensors and, more particularly, touchmode capacitive pressure sensors.

BACKGROUND OF THE INVENTION

In various industrial and commercial applications, it is desired tomeasure pressure in a hostile environment, with a miniaturized sensorhaving good stability, low power consumption, robust structure, largeover pressure protection range, and good linearity and sensitivity. Forexample, such a sensor could be used in conjunction with an RFtransponder disposed within a pneumatic tire as shown in commonly-owned,copending PCT patent application No. US98/07338 filed Apr. 14, 1998,incorporated in its entirety by reference herein. Applications such asthe pneumatic tire place additional requirements on the pressure sensordue to the need for the sensor to withstand both the normal operatingtemperature and pressure ranges and also the much higher (many times theoperating values) manufacturing temperature and pressure. For example,molding the sensor into a tire is but one illustration of an environmentwhere conventional sensors fail to meet these desired criteria.

Capacitive pressure sensors are known, and can be designed to meet manyif not all of the desired characteristics. Capacitive pressure sensorsgenerally include two capacitive elements (plates, or electrodes), oneof which is typically a thin diaphragm, and a gap between theelectrodes. When a pressure is exerted on the diaphragm, the diaphragmdeflects (deforms) and the size of the gap (in other words, the distancebetween the two capacitive elements) varies. And, as the gap varies, thecapacitance of the sensor varies. Such changes in capacitance can bemanifested, by associated electronic circuitry, as an electronic signalhaving a characteristic, such as voltage or frequency, indicative of thepressure exerted upon the sensor.

In the “normal” operation mode of a capacitive pressure sensor, thediaphragm does not contact the fixed electrode. The output capacitanceis nonlinear due to an inverse relationship between the capacitance andthe gap which is a function of pressure P. This nonlinearity becomessignificant for large deflections. Many efforts have been made to reducethe nonlinear characteristics of capacitive sensors either by modifyingthe structure of the sensors or by using special non-linear convertercircuits.

Particularly advantageous for the achievement of linearity has been thedevelopment of “touch mode capacitive pressure sensors” (TMCPS). Aparticular class of capacitive pressure sensors operate in what is knownas “touch mode”. Touch mode sensors have been disclosed, for example, inDing, et al., Touch Mode Silicon Capacitive Pressure Sensors, 1990 ASMEWinter Annual Meeting, Nov. 25, 1990, incorporated in its entirety byreference herein. They are further explained in Ko and Wang, Touch ModeCapacitive Pressure Sensors, Sensors and Actuators 2303 (1999), alsoincorporated in its entirety by reference herein.

Conventional capacitive pressure sensors normally operate in a pressurerange where the diaphragm is kept from contacting the underlyingelectrode, and normally exhibit nonlinear characteristics. This inherentnon-linearity has led to the development of many linearization schemesusing complex and costly interface circuits which include analogcircuits and amplifiers, segment linearization, microprocessor and ROMmatrix linearization, etc.

In contrast thereto, touch mode capacitive pressure sensors, operatingin the range where the diaphragm touches the insulating layer on theunderlying electrode, exhibit near linear behavior in certain pressureranges. The increased linearity is attributable to the touched area(footprint) increasing linearly with applied pressure and the increasedrigidity of the diaphragm after touch.

Furthermore, the touch mode capacitive pressure sensor has much highersensitivity (large capacitance change per unit pressure change) comparedto conventional capacitive pressure sensors. Therefore, smallenvironmentally-caused capacitance changes over time becomeinsignificant and can be neglected. This makes the touch mode device along term stable device over a wide range of environmental conditions.

These advantages are inherent with touch mode capacitive devices, nomatter what materials are used for the diaphragm and the substrate.

Generally, touch mode capacitive pressure sensors differ fromconventional capacitive pressure sensors (described hereinabove) in thatthe diaphragm element is permitted to deflect sufficiently to come intoactual physical contact with the underlying fixed capacitive element ata given pressure. Typically, a thin dielectric insulating layer on thefixed capacitive element prevents the diaphragm from electricallyshorting to the fixed capacitive element. As the pressure increases, the“footprint” of the diaphragm upon the fixed capacitive elementincreases, thereby altering the capacitance of the sensor, which can bemanifested, by associated electronic circuitry, as an electronic signalhaving a characteristic indicative of the pressure exerted upon thesensor. The major component of the touch mode sensor capacitance is thatof the touched area footprint where the effective gap is the thicknessof the thin insulator layer between the pressed-together capacitiveelements. Because of the small thickness and large dielectric constantof the isolation layer, the capacitance per unit area is much largerthan that of the untouched area which still has an added air or vacuumgap. In a certain pressure range, the touched area is nearlyproportional to the applied pressure, and results in the nearly linearC-P (capacitance-pressure) characteristics of the touch mode pressuresensor. For the range of pressures in the touch mode operation region,the sensor capacitance varies with pressure nearly linearly and thesensitivity (dC/dP) is much larger than that in the near linear regionof a normal mode device. In addition to high sensitivity and goodlinearity, the fixed element substrate provides support to the diaphragmafter it touches, thus enabling the device to have significant pressureover-load protection. In summary, the advantages of TMCPS are nearlylinear C-P characteristics, large overload protection, high sensitivityand simple robust structure that can withstand industrial handling andharsh environments.

As used herein, a “touch mode” capacitive pressure sensor includes anycapacitive pressure sensor wherein at least a portion of the operatingrange of the pressure sensor occurs while the diaphragm is in physicalcontact with the underlying capacitive element.

An early example of a capacitive touch mode pressure sensor is shown inU.S. Pat. No. 3,993,939, entitled PRESSURE VARIABLE CAPACITOR,incorporated in its entirety by reference herein. This patent disclosesa large scale version of TMCPS with a variety of diaphragmconstructions.

Some of the more recent efforts have focused on miniaturization, costreduction, and performance improvements. An example is shown in U.S.Pat. No. 5,528,452, entitled CAPACITIVE ABSOLUTE PRESSURE SENSOR,incorporated in its entirety by reference herein. This patent disclosesa sensor comprising a substrate having an electrode deposited thereonand a diaphragm assembly disposed on the substrate.

The TMCPS diaphragm can be made of different materials, such as silicon,poly-silicon, silicon nitride, polymeric materials, metal, andmetallized ceramic. Each material choice has its advantages anddisadvantages. For good stability, robust structure, and avoidance oftemperature and pressure related problems, the use of single crystalsilicon is preferred, because it has well characterized, wellunderstood, reliable and reproducible electrical and mechanicalproperties. The aforementioned U.S. Pat. No. 5,528,452 discloses apreferred embodiment with a single crystal silicon diaphragm, which iselectrostatically bonded (anodic bonding) to a glass substrate. Althoughthis provides a simple construction which avoids prior art problems withsealing of the vacuum chamber contained between the capacitive elements,it still requires special techniques to fill the gap around theelectrical feedthrough from the fixed electrode inside the vacuumchamber to the external electrical connection. The fixed electrode andthe connected feedthrough consist of a thin layer of metal deposited onthe surface of the glass substrate, covered by an insulating layer. Thefeedthrough creates a raised line which must pass under the sealing edgeof the silicon diaphragm assembly. In order to seal around thefeedthrough, a groove is cut in the sealing edge of the silicondiaphragm assembly. With proper shaping of the feedthrough and groove,and with proper alignment, a suitable heat treatment will cause theglass insulating layer to deform and seal the space around thefeedthrough in the diaphragm assembly groove.

All-silicon capacitive pressure sensors are characterized by highpressure sensitivity, low mechanical interference and low temperaturesensitivity. They can operate up to a temperature of about 300° C., andremain almost free of hysteresis.

Drift exhibited by silicon-to-glass capacitive pressure sensors isbelieved to be caused by mismatch between the thermal expansioncoefficients of the glass and the silicon, and the stress built duringfabrication. Other problems can arise under temperature extremes whichmay cause the glass or glass frit to outgas. Using silicon-to-siliconfusion bonding technology, a single crystal capacitive pressure sensorcan be realized. For silicon-to-silicon bonded structures, both wafershave the same thermal expansion coefficients, and a better thermalstability is expected than with the silicon-to-glass structure. Usingthe silicon fusion bonding method, an ultra-stable, high temperature,capacitive pressure sensor can be made.

Silicon fusion bonding is a known technique for bonding together siliconcomponents, either directly silicon-to-silicon, or via an intermediarysilicon oxide layer. The latter technique is disclosed, for example, inU.S. Pat. No. 3,288,656, entitles SEMICONDUCTOR DEVICE, incorporated inits entirety by reference herein. A limitation of this technique is thatthe surfaces to be bonded must be microscopically smooth in order toachieve the intimate contact needed to form good silicon-to-silicon orsilicon-to-silicon oxide fusion bonds.

An example of a capacitive pressure sensor with an all-silicon vacuumchamber fabricated using silicon fusion bonding can be seen in U.S. Pat.No. 5,656,781, entitled CAPACITIVE PRESSURE TRANSDUCER STRUCTURE WITH ASEALED VACUUM CHAMBER FORMED BY TWO BONDED SILICON WAFERS, incorporatedin its entirety by reference herein. This sensor avoids the problems ofsealing around a feedthrough by placing the fixed electrode on asubstrate adjacent to the silicon diaphragm but outside the siliconvacuum chamber. As such, the sensor cannot function in a touch modesince ambient pressure deflects the diaphragm away from the fixedelectrode.

Another example of an all-silicon, touch mode capacitive pressure sensoris shown in U.S. Pat. No. 5,706,565, entitled METHOD FOR MAKING ANALL-SILICON CAPACITIVE PRESSURE SENSOR, incorporated in its entirety byreference herein. This patent discloses a sensor with a vacuum chamberformed as a cavity etched into a single crystal silicon wafer doped tobe conductive, has an insulating oxide layer on top of the wafer, and aconductive heavily-doped (P+) single crystal silicon diaphragm which isbonded on top of the oxide layer. Among the problems inherent in thisdesign are the expense of a relatively complicated process and “straycapacitance” effects. The patent refers to “conventional wafer-to-waferbonding techniques” for bonding the diaphragm to the substrate. Theconventional wafer-to-wafer bonding technique known to those practicedin the art is silicon fusion bonding, which requires microscopicallysmooth bonding surfaces, as mentioned hereinabove. In order to achievesuch a smooth surface on a heavily doped silicon wafer, the conventionaltechnique uses ion bombardment for the P+ doping, rather than diffusion,because the diffusion process roughens the silicon wafer surface.Unfortunately, ion bombardment doping is much more time consuming, andtherefore more expensive, than diffusion doping.

The term “stray capacitance” refers to capacitance other than thepressure-sensing capacitance, occurring elsewhere in the sensor or itsmeasuring circuit. In the device of the U.S. Pat. No. 5,706,565mentioned hereinabove, the sensing capacitance occurs between theconductive diaphragm and the fixed electrode (the conductive substrateat the bottom of the cavity), which are separated by a thin dielectriclayer. The conductive silicon diaphragm is bonded to an insulating oxidelayer on top of the conductive silicon substrate and this forms a secondcapacitor in parallel with the sensing capacitor. The second capacitorprovides stray capacitance with a value which is mainly determined bythe oxide layer characteristics and by the total area of contact betweenthe diaphragm and the oxide layer. In order to achieve a good bond, thissurface area is typically large enough to produce stray capacitancevalues more than an order of magnitude larger than the pressure sensingcapacitance values.

Problems with capacitive pressure sensors can arise when the sensor mustoperate over a wide range of temperatures and over a wide range ofpressures. Moreover, in some instances, it is essential that thepressure sensor simply survive temporary extremely hostile temperaturesand/or pressures, even though it is not operating. For example, moldinga pressure sensor into a tire during the fabrication of the tire is anexample of a situation where the pressure sensor must survive extremelyhostile ambient conditions.

An absolute pressure sensor should also preferably be stable, and freefrom base line drift problems, both short term and long term. Thesecharacteristics are particularly important for applications such assensors disposed inside tires, where ambient conditions varysignificantly and access for maintenance and calibration is limited andrelatively costly.

OBJECTS OF THE INVENTION

It is an object of this invention to provide a force sensor and amanufacturing method for a force sensor (such as a capacitive pressuresensor) as defined in one or more of the appended claims and, as such,having the capability of being constructed and manufactured toaccomplish one or more of the following subsidiary objects.

It is an object of this invention to provide a force sensor and amanufacturing method for a force sensor (such as a capacitive pressuresensor) which has long term stability, and good linear sensitivity, evenin harsh environments, both in operation and in OEM application of thesensor in manufactured goods, e.g., such as building the sensor into therubber of a pneumatic tire, and utilizing the sensor during operation ofthe tire.

It is an object that the sensor be rugged enough to survive and operateaccurately and reliably in these harsh conditions.

It is a further object of this invention to provide a force sensor and amanufacturing method for a force sensor (such as a capacitive pressuresensor) which maintains a hermetic seal in the sensing cavity, whileproviding an isolated, buried electrical feedthrough to the fixedelectrode in the sensing cavity.

It is a further object of this invention to provide a force sensor and amanufacturing method for a force sensor (such as a capacitive pressuresensor made with a silicon substrate and diaphragm) which is costreduced by providing a means for silicon fusion bonding two siliconwafer surfaces, at least one of which is heavily doped by diffusion.

It is a further object of this invention to provide a force sensor and amanufacturing method for a force sensor (such as a capacitive pressuresensor made with a silicon substrate and diaphragm) which improvessensor stability and accuracy by minimizing stray capacitance effects,and by providing a way for interface circuits to utilize an on-chipreference capacitor to minimize ambient temperature effects on sensorsensitivity.

SUMMARY OF THE INVENTION

According to the invention, a first method of fabricating siliconcapacitive sensors, comprises providing a first silicon wafer and asecond silicon wafer; etching a buried electrical feedthrough groove inthe first silicon wafer; etching a sensing cavity and a contact cavity,each cavity connected to an opposing end of the groove; forming acontinuous and connected conductive area in the bottoms of the grooveand the cavities; forming a P+ conductive diaphragm layer on the secondsilicon wafer by means of diffusion doping, then preparing the surfaceof the diaphragm layer for bonding by polishing with achemical-mechanical polishing (CMP) process; then bonding the first andsecond wafers together using a silicon fusion bonding (SFB) technique;dissolving the second silicon wafer except for the diaphragm; etchingopen a window through the diaphragm layer to the fixed electrode contactcavity on the first silicon wafer; and finally dicing the plurality ofsensors formed by this process.

As an optional extra step, the first process can include a step offorming an oxide layer over the conductive area in the bottom of thesensing cavity, thereby forming a dielectric layer to allow touch modeoperation of the capacitive sensor formed by this method. In the samestep, an insulating layer of oxide would also be formed over theconductive area in the bottom of the groove and extending into thesensing cavity to provide a continuous insulating layer over theconductive areas in the cavity and buried feedthrough groove.

Another optional step seals the buried feedthrough groove by depositingLTO (low temperature oxide) over the groove exit to the contact window.Doing this in a vacuum creates a vacuum reference chamber out of thesensing cavity, allowing the sensor to read absolute pressure. Leavingthis step out would create a differential pressure sensor. Aftercreating a LTO layer, windows must be opened above the electricalcontacts, and optionally over the sensing diaphragm.

Another optional step provides a reference capacitor on the same chip,for reduced temperature sensitivity, by forming the reference capacitorusing a conductive area near the surface of the substrate for areference capacitor bottom electrode, establishing an electricalconnection to a reference capacitor bottom electrode contact, using theoxide layer as a fixed-gap reference capacitor dielectric, and the topelectrode is the diaphragm layer which will not move with pressure overthe reference capacitor area because there is no cavity.

Another optional step provides better electrical connections to the chipby depositing a metal layer over the electrical contacts on the chip.

According to the invention, a second method (simplified from the firstmethod) of fabricating silicon capacitive sensors, comprises providing afirst silicon wafer and a second silicon wafer; preparing the firstsilicon wafer with a thick layer of oxide on one side, with thethickness determined by a designed gap of a sensing cavity; forming thesensing cavity by etching a designed cavity shape completely through theoxide layer; forming a P+ conductive diaphragm layer on the secondsilicon wafer by means of diffusion doping; then preparing the surfaceof the diaphragm layer by polishing with a chemical-mechanical polishing(CMP) process before bonding the first and second wafers together usinga silicon fusion bonding (SFB) technique; dissolving the second siliconwafer except for the diaphragm layer; etching through the diaphragmlayer, stopping at the underlying oxide layer to create a grove aroundthe cavity and extending out to one side of the chip, so that the groovedefines the extent of the sensing diaphragm (with a connecting path to adiaphragm contact area), and electrically isolates these areas from aremainder of the diaphragm layer; etching a window through the diaphragmlayer and the oxide layer, stopping at the underlying first siliconwafer, to create a fixed electrode contact cavity; and finally dicingthe plurality of sensors which are formed by this process.

As an optional extra step for the second method, the first process caninclude a step of forming an oxide layer over the conductive area in thebottom of the sensing cavity, thereby forming a dielectric layer toallow touch mode operation of the capacitive sensor formed by thismethod.

Another optional step in the second method uses the area covered by theremainder of the diaphragm layer (i.e., not over the sensing cavity) asan on-chip reference capacitor with the substrate as a bottom electrode(shared with the sensing capacitor), with the solid oxide layer as afixed dielectric, and with the remainder of the diaphragm layer as a topelectrode.

As in the first method, another optional step provides better electricalconnections to the chip by depositing a metal layer over the electricalcontacts on the chip.

Two techniques are features of the sensors and manufacturing methods ofthis invention.

The buried feedthrough technique utilized in the first method, describedhereinabove, can be applied to any process needing to feed an electricalconnection into a sealed silicon cavity. The buried feedthrough consistsof a conductor in a shallow groove which is almost filled with anoptional covering insulating oxide layer. The gap between the top of theinsulator and the second silicon wafer which is bonded over the grooveand cavity, can then be sealed with LTO.

The second special technique of this invention is a method for forming asilicon-to-silicon fusion bond (SFB) wherein at least one of the twosurfaces to be bonded has been heavily boron-doped by means ofdiffusion, which is a less-costly way of doping, but creates a roughsilicon surface unsuitable for good SFB joints. The technique is toprepare each doped surface for SFB by polishing the surface in aChemical-Mechanical Polishing (CMP) process.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made in detail to preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings (Figures). The drawings are intended to be illustrative, notlimiting. Although the invention will be described in the context ofthese preferred embodiments, it should be understood that it is notintended to limit the spirit and scope of the invention to theseparticular embodiments.

Certain elements in selected ones of the drawings may be illustratednot-to-scale, for illustrative clarity. The cross-sectional views, ifany, presented herein may be in the form of “slices”, or “near-sighted”cross-sectional views, omitting certain background lines which wouldotherwise be visible in a true cross-sectional view, for illustrativeclarity.

Elements of the figures are typically numbered as follows. The mostsignificant digits (hundreds) of the reference number corresponds to thefigure number. Elements of FIG. 1 are typically numbered in the range of100-199. Elements of FIG. 2 are typically numbered in the range of200-299. Similar elements throughout the drawings may be referred to bysimilra reference numerals. For example, the element 199 in a figure maybe similar, and possibly identical to the element 299 in an otherfigure. In some cases, similar (including identical) elements may bereferred to with similar numbers in a single drawing. For example, eachof a plurality of elements 199 may be referred to individually as 199 a,199 b, 199 c, etc., and the complete set of elements 199 a, 199 b, 199c, etc. may be referred by the group reference 199. Such relationships,if any, between similar elements in the same or different figures willbecome apparent throughout the specification, including, if applicable,in the claims and abstract.

The structure, operation, and advantages of the present preferredembodiment of the invention will become further apparent uponconsideration of the following description taken in conjunction with theaccompanying drawings, wherein:

FIG. 1A is a side cross sectional view of a single chip portion of waferA after Step 1 of the first SFB TMCPS manufacturing process, taken on aline 1K—1K through FIG. 1L, according to the invention;

FIG. 1B is a side cross sectional view of a single chip portion of waferA after Step 2 of the first SFB TMCPS manufacturing process, taken on aline 1K—1K through FIG. 1L, according to the invention;

FIG. 1C is a side cross sectional view of a single chip portion of waferA after Step 3 of the first SFB TMCPS manufacturing process, taken on aline 1K—1K through FIG. 1L, according to the invention;

FIG. 1D is a side cross sectional view of a single chip portion of waferA after Step 4 of the first SFB TMCPS manufacturing process, taken on aline 1K—1K through FIG. 1L, according to the invention;

FIG. 1E is a side cross sectional view of a single chip portion of waferA after Step 5 of the first SFB TMCPS manufacturing process, taken on aline 1K—1K through FIG. 1L, according to the invention;

FIG. 1F is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 5 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1G is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 7 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1H is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 8 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1I is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 9 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1J is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 10 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1K is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 11 of the first SFB TMCPSmanufacturing process, taken on a line 1K—1K through FIG. 1L, accordingto the invention;

FIG. 1L is a partially cut-away three dimensional view of a finished SFBTMCPS at the completion of the first SFB TMCPS manufacturing process,according to the invention;

FIG. 2A is a side cross sectional view of a single chip portion of waferA after Step 2 of the second SFB TMCPS manufacturing process, taken on aline 2F—2F through FIG. 2G, according to the invention;

FIG. 2B is a side cross sectional view of a single chip portion of waferA after Step 3 of the second SFB TMCPS manufacturing process, taken on aline 2F—2F through FIG. 2G, according to the invention;

FIG. 2C is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 4 of the second SFB TMCPSmanufacturing process, taken on a line 2F—2F through FIG. 2G, accordingto the invention;

FIG. 2D is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 5 of the second SFB TMCPSmanufacturing process, taken on a line 2F—2F through FIG. 2G, accordingto the invention;

FIG. 2E is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 6 of the second SFB TMCPSmanufacturing process, taken on a line 2F—2F through FIG. 2G, accordingto the invention;

FIG. 2F is a side cross sectional view of a single chip portion of waferA assembled with wafer B after Step 7 of the second SFB TMCPSmanufacturing process, taken on a line 2F—2F through FIG. 2G, accordingto the invention;

FIG. 2G is a top plan view of a finished SFB TMCPS at the completion ofthe second SFB TMCPS manufacturing process, according to the invention;and

FIG. 3 is a side cross sectional view of an example of achemical-mechanical polishing (CMP) process, according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

A silicon capacitive pressure sensor according to the present inventionhas the advantages of good stability over time, low power consumption,robust structure, large over pressure tolerance, large range, increasedlinearity and sensitivity, and improved temperature characteristicsallowing simplified reading circuitry. The disclosed fabrication methodsallow for reduced manufacturing costs due to reduced process time,simplified process steps, and improved process yield.

The present invention is directed to the design, fabrication andpackaging of silicon capacitive pressure sensors for industrial andother applications where time stable operation over wide measurementranges in difficult environments is required. The present sensorpreferably operates in the touch mode with a zero suppression feature.However, non-touch mode operation is also usable. The present designapproaches and manufacturing techniques result in unique performance.

While the present invention is particularly directed to the art of touchmode capacitive absolute pressure sensors, and will thus be describedwith specific reference thereto, it will be appreciated that theinvention may have usefulness in other fields and applications such asfor acceleration and force sensors, and for diaphragm type actuators.

The structure, operation, and advantages of the present preferredembodiments of the invention will become further apparent uponconsideration of the following description taken in conjunction with theaccompanying drawings.

FIG. 1L illustrates most of the elements of a first preferred embodimentof an all-silicon touch mode capacitive pressure sensor (TMCPS) 100based on silicon fusion bond (SFB) technology. It consists of aconductive, deformable single crystal silicon diaphragm 152 withthickness “h” forming the top capacitive element (moving electrode) forboth a sensing capacitor 140 and an optional reference capacitor 141.The diaphragm 152 is silicon fusion bonded to the surface of a secondsingle crystal silicon wafer 102 (wafer A), via an intermediary oxidelayer 104 a″. the wafer A (102) has several features including a sensingcavity 108 and a contact cavity 110, both of depth “g” below the wafer102 surface. Connecting the sensing cavity 108 and the contact cavity110 is a groove 106 of a lesser depth “d”. Optional features, shown inFIG. 1L, are a reference capacitor groove 107 a, a reference capacitorcontact groove 107 c, and a reference capacitor feedthrough groove 107 bwhich connects the reference capacitor groove 107 a to the referencecapacitor contact groove 107 c. These three optional grooves 107 (107 a,107 b and 107 c) are all at a depth “d1” which is less than orapproximately the same as the depth “d” of groove 106. The shaded areasin the bottom of the cavities and grooves represent areas 112, 113 ofthe silicon substrate which have been rendered conductive to form asensing capacitor fixed electrode 112 a, a fixed electrode contact 112c, and a “buried feedthrough” 112 b which electrically connects thefixed electrode 112 a and its external contact 112 c. The conductivearea 113 is optional if a reference capacitor is desired, and consistsof a reference capacitor bottom electrode 113 a, a reference capacitorbottom electrode contact 113 c, and a feedthrough 113 b whichelectrically connects the reference capacitor bottom electrode 113 a, toits external contact 113 c. Three metal electrical contact pads areshown deposited on top of their corresponding contacts: the fixedelectrode contact pad 130 (above contact 112 c), the optional referencecapacitor contact pad 131 (above optional contact 113 c), and the topelectrode contact pad 132 (providing a metal connection pad for theconductive silicon layer 152 which comprises the sensing capacitor'sdiaphragm/top electrode and also the optional reference capacitor's topelectrode). Not shown in FIG. 1L are insulating layers which are formedon top of the bottom electrodes 112 a (and optionally 112 c), andpartially filling the groove(s) 106 (and optionally 107 b) on top of thefeedthrough(s) 112 b (and optionally 113 b).

CHEMICAL MECHANICAL POLISHING

As mentioned hereinabove, the diaphragm 152, made from a single crystalsilicon wafer 150 (“wafer B”), is bonded to another single crystalsilicon wafer 102 (“wafer A”) using silicon fusion bonding (SFB).Although SFB is a well-established bonding technique, its applicabilityhas been limited in the prior art to bonding silicon and/or oxidizedsilicon surfaces which must be microscopically smooth in order toachieve a strong, durable, hermetically-sealed bond. This smoothnessrequirement is routinely met for the top surface of wafers such as waferA (102), whether it is doped as N or P-type silicon, and with or withoutan insulating oxide layer such as layer 104 a″. The problem in the priorart has occurred when the silicon surface to be bonded needs to ba aheavily doped P+ layer such as the diaphragm 152. Heavily boron dopedsilicon (P+) is commonly used as an etch-stop layer to makemicrostructures, such as diaphragms and beams. The dimension of thestructures made from the P+ layer can be precisely controlled, and theP+ layer is suitably conductive to allow the diaphragm 152 to be acapacitor electrode without metalizing. However, silicon fusion bondingof P+ is difficult. A known, low cost P+ doping process is heavy borondoping by diffusion, but this diffusion process creates a rough surfaceon the silicon wafer, with a high density of pits and dislocation lineswhich make the surface unsuitable for SFB. The pits and lines greatlyreduce the wafer-to-wafer contact area, hence reducing the siliconfusion bonding force. The conventional solution has been to do thedesired P+ doping by the much more time-consuming, and therefore moreexpensive, process of ion bombardment.

An important feature of this invention is a step in the manufacturingmethod which utilizes chemical-mechanical polishing (CMP) on the roughsurfaced side 152 of wafer B 150 after using diffusion doping to createthe P+ diaphragm layer 152 in the wafer B (150). Although the CMPprocess is well known in the art, this invention has developed a novelapplication of CMP to make possible a cost-reduced process for joiningP+ silicon wafer surfaces. For the application of this invention, theCMP process and equipment are illustrated in FIG. 3. The wafer 350(compare 150) which is to be polished, is held from the top in arotating polishing head 360, and pressed flat against the rotatingpolishing plate 362. The chemical-mechanical polishing medium is aslurry 370 which is supplied to the surface of the polishing plate 362in a way which maintains a suitable layer of slurry 370 between thepolishing plate 362 and wafer 350. A slurry 370 such as SC-1 by Cabot,with an aggregate particle size of 100 nm and primary particle size of30 nm can be used. Since the sorry contains both abrasive particles anda chemical etchent, the wafer 350 is subjected to both mechanicalwearing and chemical etching simultaneously during polishing.Protrusions of different heights on the surface of the silicon wafer 350will experience different pressures and consequently different wearingand etching. The difference in the removal rate will lead to smoothingon the surface. In a typical trial of the invented process, after 3minutes of such CMP polishing the polished surface of wafer 350 had amicro-smoothness compatible with the surface of a blank device-gradedwafer. After CMP, cost-effective diffusion doped P+ silicon wafersurfaces such as 152 become bondable by standard SFB techniques.

The annealing process for silicon fusion bonding limits the selection ofthe bottom electrode(s) 112 a (and optionally 113 a) of the capacitivesensor 140 and the optional reference capacitor 141. The same is truefor the other conductive areas: the feedthrough(s) 112 b (and optionally113 b) and the contact(s) 112 c (and optionally (113 c). The conductiveareas cannot use common metals, such as aluminum or platinum (as iscommonly done in a silicon-glass structure) since the SFB annealingtemperature is normally higher than the eutectic temperature of mostmetals with the silicon substrate material. Besides furnacecontamination considerations, the metal can alloy with silicon at theSFB annealing temperatures to cause high resistivity, open circuits, anddifficulty to wire bond in the sensor packaging. A boron heavilydiffused layer (P+) on the N-type silicon substrate 102 is used for theconductive areas 112 (and optionally 113) of the substrate 102 as itwill provide sufficiently low resistivity after the final SFB annealingprocess. An added advantage is that the P+ conductive areas can also beeasily wire-bonded even without metalization.

THE BURIED FEEDTHROUGH

The “buried feedthrough” 112 b is an important feature of thisinvention, and is best seen illustrated in cross section view in FIG.1I. A touch mode capacitive pressure sensor needs an electricalconnection 112 b between the bottom electrode 112 a in the cavity 108and the contact 112 c for connection to an external interface circuit(not shown). For the preferred embodiment 100 which can measure absolutepressure, the cavity 108 must be evacuated and hermetically sealed tothe diaphragm 152. Even though the conductors 112 of this invention areformed by a heavily doped boron diffusion process, rather than metaldeposition, because of doping concentration dependent oxidation there isusually a step generated in the doped feedthrough region if thefeedthrough is on the silicon surface, even when the feedthrough iscovered by an insulating layer of oxide 114 or 104 a″. This would causedifficulties for silicon fusion bonding and hermetic sealing. In theburied feedthrough design of this invention, the feedthrough 112 b is P+diffusion doped in the bottom of a shallow groove 106 of depth d′ (e.g.,approximately 2.1-3.1 μm) below the SFB (top) surface of the oxide layer104 a″, and then covered in the groove 106 with an insulating layer ofoxide 114 b of thickness t2 (e.g., approximately 0.2-0.3 μm) which onlypartially fills the depth of the groove 106, leaving a groove gap 106′.A subsequent process step can be used to hermetically seal the vacuumcavity of the sensor by depositing a layer 120 of low temperature oxide(LTO) (e.g., 400 mTorr, 450° C.) if an absolute pressure TMCPS isdesired. By omitting the LTO layer 120 (especially the sealing portion120 b), the groove gap 106′ can be used as a channel for a secondpressure in a differential pressure version of a TMCPS. It should benoted that, unlike the prior art, this buried feedthrough techniquepromotes good silicon fusion bonding without any wafer-to-waferalignment requirements.

STRAY CAPACITANCE, FLOATING ELECTRODES, REFERENCE CAPACITORS

Two features of this invention ensue from sensor design andmanufacturing methods which address the problems of stray capacitance insilicon fusion bonded touch mode capacitive pressure sensor (SFB TMCPS).These features are illustrated, for example, in FIG. 1L, and comprise afloating bottom electrode 112 a and buried feedthrough 112 b, and alsothe optional addition of a reference capacitor 141 on the same chip 100as the sensing capacitor 140.

It has been observed in the art that one drawback of silicon fusionbonded capacitive pressure sensors is that they have large zero-pressurecapacitance, which makes the sensed capacitance much less than thebackground capacitance and thus limits applications of some capacitiveinterface circuits. For example, a typical SFB TMCPS has a measuringsensitivity of 0.086 pF/psi in a linear region from 30-70 psi, but thezero-pressure capacitance can be as high as 7.3 pF. The largezero-pressure capacitance originates from the relatively large SFBbonding area and the insulating oxide layer 104 a″ with a largedielectric constant which lies between the diaphragm layer 152 and thesubstrate 102 to which it is bonded. The bonded area creates an extracapacitor (creating “stray capacitance”) which lies indistinguishably inparallel with the sensing capacitor 140 but cannot be electricallyaccessed separately. At zero pressure, since the deflection of thediaphragm 152 is small, the gap distance between diaphragm 152 and thebottom electrode 112 a is large. Therefore the capacitance of theair-gap capacitor contributes a small part to the overall capacitance atzero pressure so the zero pressure capacitance is mainly determined bythe stray capacitance created by the bonding area. For a given set ofmaterial properties and thicknesses, the stray capacitance will beroughly proportional to the size of the bonded area between thediaphragm 152 and the oxide layer 104 a″. Attempts to minimize thisbonding area must be balanced against a bonding area size big enough toensure a hermetic seal and good mechanical support of the diaphragm 152.

Besides minimizing the bonding area, another way to reduce straycapacitance in an SFB TMCPS is to reduce the conductivity of thesubstrate 102 and to electrically isolate (“float”) the bottom electrode112 a. As a feature of the first preferred embodiment of this invention,represented by FIG. 1L, this is accomplished by using N-type silicon forthe substrate 102 wafer A, and by creating a floating bottom electrode112 a through these of P+ doping for only the area of the electrode 112a and its electrical feedthrough 112 b. Also, the sensing area (of theelectrode 112 a) is maximized relative to the total chip 100 area, andthe non-sensing area of the feedthrough 112 b (which contributes to thestray capacitance) is minimized by using a narrow groove 106, recessedbelow the surface with a partial air/vacuum gap (106′ in FIG. 1I). Thusthe floating electrode 112 a design with buried feedthrough 112 b is anadvantageous feature of this invention which reduces stray capacitanceeffects.

Another approach to dealing with stray capacitance involves the use ofreference capacitors to attempt to null out the zero pressurecapacitance. In much of the prior art, the reference capacitor has beenincluded in the interface circuits, but this can require complexcircuitry and even then may not assure that the reference capacitor inthe interface circuit changes with ambient conditions in the same way asthe stray capacitance in the sensor. These problems are avoided when thereference capacitor is formed on the same silicon chip as the sensingcapacitor and its accompanying stray capacitance. An advantageousfeature of this invention is sensor designs which enable theimplementation of a reference capacitor (e.g., 141, 241) on the samesilicon chip (e.g., 100, 200) as the sensing capacitor (e.g., 140, 240).

Interface circuits, such as the CP10, CP11 and CP12 (portions of whichare disclosed in THE commonly owned co-pending PCT patent applicationentitled DUAL CAPACITIVE INTERFACE CIRCUIT (Attorney's Docket No.DN1999-136), which are CMOS switched-capacitor C-V and C-F converters,can be used to overcome the obstacles presented by the large zeropressure or stray capacitance. Such converters have the ability to nullout the zero pressure capacitance and to adjust the sensitivity andoffset independently. The outputs of both converters are proportional tothe charge difference between the measuring capacitor and a referencecapacitor, which can be expressed as: $\begin{matrix}{V = \frac{{V_{g}C_{x}} - {V_{o}C_{o}}}{C_{f}}} & (1)\end{matrix}$

and

F=k(V_(g)C_(x)−V_(o)C_(o))  (2)

where V is an interface circuit's DC output voltage, F is an interfacecircuit's output frequency, C_(x) and C_(o) are the sensed capacitanceand the reference capacitance, respectively, V_(g) and V_(o) are two DCvoltages that can be used to control the gain, and C_(f) is a constantcapacitance, which can be used to adjust the circuit's sensitivity. Itcan be seen from equation (1) that if a smaller C_(f) is used, then alarger voltage sensitivity can be obtained. The reference capacitorbuilt into the sensor structure can be used as the C_(o) in theinterface circuit. Since it is fabricated and operated under the sameconditions as the sensing capacitor C_(x), the built-in referencecapacitor has the same temperature characteristics as the sensingcapacitor. This property is beneficial for the temperature stability ofthe sensor when it is used with a converter such as the CP-10, CP-11, orCP-12. In a test with a sensor 200 (see FIG. 2G) made according to thisinvention using the built-in reference C_(o) (capacitor 241) instead ofan external C_(o), the sensitivity in the linear touch mode operationrange is 40 mV/psi where the gain setting capacitor C_(f) in a CP-10interface is 10 pF. The temperature performance was improved to arelative error of ±0.66% in the temperature range from 27° C. to 100°C., compared to ±4.1% for a similar sensor using an external referenceC_(o) capacitor (and without a built-in reference capacitor 241).

A PREFERRED EMBODIMENT OF A SFB TMCPS MANUFACTURING PROCESS

Referring to the drawings, FIGS. 1A to 1K illustrate representativesteps of a first preferred embodiment 100 of a structure andmanufacturing process design for a touch mode capacitive pressure sensor(TMCPS) based on silicon fusion bonding (SFB) technology. The resultingsensor 100 embodiment can be seen in FIG. 1L, shown in a partiallycutaway 3D view. Although these figures illustrate a single sensor atvarious stages in the process, it should be understood that theseprocess steps are applied simultaneously to all the plurality ofsensors, not shown, but contained within the bounds of the same waferassembly which contains the illustrated sensor.

A first exemplary SFB TMCPS fabrication process, for fabricating aplurality of SFB TMCPS sensors according to the invention, includes thefollowing process steps. Although the steps are numbered for convenientreference, it is within the scope of this invention to fabricate asensor using some or all of these steps, and in any order. It shouldalso be understood that the labeling of the steps is arbitrary, for theconvenience of this explanation, so that a given “step” may actuallyinclude several discrete manufacturing processes or process stages.

Step 0. Begin with two single crystal silicon wafers: Wafer A (102) andWafer B (150). Wafer A (102) is, for example, an N-type silicon wafer,<100> orientation, with a resistivity of 5-10 ohm-cm. Wafer A (102) isused as the substrate for the sensor 100 and includes a cavity for thebottom (fixed) electrode 112 a of each sensor 100, plus various otherfeatures as will become evident from the following description. Wafer B(150) is, for example, a P-type silicon wafer, <100> orientation, with aresistivity of 2-5 ohm-cm. Wafer B (150) is used to form the diaphragmcapacitive element (electrode) 152 of each sensor 100.

Step 1. FIG. 1A illustrates Wafer A (102) with a thin (e.g.,approximately 5000 Å) layer of oxide 104 (104 a, 104 b) thermally grownon both flat sides (to prevent wafer buckling), to be used as an etchingmask.

Step 2. FIG. 1B illustrates a feedthrough groove 106 which has beenetched into Wafer A (102) for the electrical feedthrough 112 b from thefixed electrode 112 a in the cavity 108 to the electrical contact 112 coutside of the cavity 108. Using “Mask 1”, the oxide 104 a is patterned(using known techniques) followed by a silicon etch (e.g., usingSF6-based plasma silicon etching) to form a feedthrough groove 106 ofinitial depth “d” which is, for example, approximately 0.1 μm deep inthe silicon below the oxide layer.

If the sensor 100 is to have an optional reference capacitor 141 (seeFIG. 1L), then this Step 2 would also include etching grooves 107 (107a, 107 b, 107 c) for the reference capacitor groove 107 a, the referencecapacitor feedthrough groove 107 b, and the reference capacitor contactgroove 107 c. If “Mask 1” is made to include the grooves 107 along withthe groove 106, then all of these grooves 106, 107 could be patternedand etched simultaneously, and the grooves 107 would be at a depth belowthe silicon 102 surface measuring “d1” which is approximately the sameas depth “d” of the feedthrough groove 106. In an alternate embodiment,a separate “Mask 1 a” could be used for the grooves 107 after thepattern & etch is completed for “Mask 1”. In this embodiment, the “Mask1 a” would be used to pattern the oxide layer 104 a followed by ashorter-time silicon etch, or even no etch, in order to produce grooves107 which are at a depth “d1” which is less than groove 106 depth “d”,and could even be at zero depth, i.e. exposing the surface of thesilicon 102 below the patterned grooves in the oxide layer 104 a.

Step 3. FIG. 1C illustrates a sensing cavity 108 and a contact cavity110 which have been etched so that they connect via the feedthroughgroove. Using “Mask 2”, the oxide is patterned followed by a siliconetch. The depth of the silicon etch is controlled to achieve an initialsensing cavity depth “g” which will ultimately (see Step 4) determinethe desired sensing capacitor gap “g′” (electrode separation distance,e.g., 6 μm). Optionally, over-etch to create a step or, alternatively, arounded-off edge around the periphery of the cavity 108. Finally, removethe oxide 104 a and thermally grow another thin (e.g., approximately5000 Å) oxide layer 104 a′ for use as a diffusion mask.

Step 4. FIG. 1D illustrates the connected conductive P+ areas 112 (112a, 112 b, 112 c) formed in the silicon at the bottom of the sensingcavity 108, the feedthrough groove 106, and the contact cavity 110,respectively. It should be noted that the P+ conductive area 112 bincludes portions which are formed in the vertical walls of the sensingcavity 108 and the contact cavity 110 in order to connect area 112 a toarea 112 b to area 112 c (also see FIG. 1L). Using “Mask 3”, firstpattern the oxide layer 104 a′, and then heavily-dope (P+) the exposedsilicon by boron diffusion (e.g., using solid source BN at approximately1120° C. for one hour) to form the conductive areas 112. In order to getgood step coverage over the sensing cavity 108 of a few microns deep, athick photoresist may be used.

If the sensor 100 is to have an optional reference capacitor 141 (seeFIG. 1L) then this Step 4 would also include forming the conductive P+areas 113 (113 a, 113 b, 113 c) in the silicon at the bottom of thereference capacitor groove 107 a, the reference capacitor feedthroughgroove 107 b and the reference capacitor contact groove 107 c,respectively. If “Mask 3” is made to include the areas 113 along withthe areas 112, then all of these areas 112, 113 could be patterned andP+ doped simultaneously.

After P+ doping, remove the boron glass which grows during the borondiffusion process (e.g., heat treat in an oxygen atmosphere to softenthe borosilicate glass so that it can be removed by etching in BHF), andthen strip off the now-contaminated oxide layer 104 a′.

Step 5. FIG. 1E illustrates the formation of new insulating oxide layers104 a″, 114 a, 114 b, and 114 c over the wafer A (102) top surface, thebottom (fixed) electrode 112 a, the buried feedthrough 112 b, and thefixed electrode contact 112 c, respectively. It should be noted that anyof these new “oxide” layers could optionally be nitride or a combinationof silicon oxide and silicon nitride in keeping with common practice toreduce stress. Using suitable masks (Masks 4 a, 4 b, etc. as needed) andknown techniques (e.g., wet oxidation at 950° C.) grow a thickinsulating oxide layer 104 a″ (e.g., thickness “t3” of 2-3 μm) on thetop surface of wafer A (102). Similarly grow a thin insulating oxidelayer 114 b (e.g., thickness “t2” of 0.2-0.3 μm) over the buriedfeedthrough 112 b. And similarly grow an insulating oxide layer 114 a(e.g. thickness “t1” of 0.2-0.6 μm) over the fixed electrode 112 a. Itshould be noted that these thicknesses are important and should becalculated to meet the design criteria for the specific TMCPS beingmanufactured. There is also an oxide layer 114 c grown over the fixedelectrode contact 112 c. The thickness of this layer is not important asit will be stripped off again in a later step. It can be any convenientthickness, such as 0.1-3.0 μm.

The oxide layer 114 a is the dielectric layer between the sensingcapacitor's electrodes 112 a and 152, and therefore partly determinesthe capacitance value. The depth “g′” measured from the top of layer 104a″ down to the top of the layer 114 a is determined by a combination ofthe initial sensing cavity depth “g” (see FIG. 1C) and the layerthicknesses “t1” and “t3”. The depth “g′” becomes the effective sensingcapacitor gap, which is an important TMCPS design parameter determiningthe TMCPS performance characteristics. The gap is easily adjusted,independently of other sensor characteristics, for different sensordesigns by changing the silicon etching time in Step 3 to vary theinitial sensing cavity depth “g”.

Besides affecting the gap “g′”, the oxide layer 104 a″ primarilydetermines the degree of insulation between wafer A (102) and the P+conductive diaphragm 152. It also plays a role in determining straycapacitance, as described hereinabove.

Similar to the cavity depth “g′”, the groove depth “d′” is determined bya combination of the initial groove depth “d” (see FIG. 1B) and thelayer thicknesses “t2” and “t3”. The depth “d′” should be adjusted tomake a suitably sized channel into the sensing cavity 108 if the sensor100 is to be used as a differential pressure transducer. On the otherhand, the depth “d′” should be adjusted to leave a more shallow gap sothat it can be more readily sealed off (see FIG. 1I) if the sensor 100is to be used in its preferred application as an absolute pressuresensor.

If the sensor 100 is to have an optional reference capacitor 141 (seeFIG. 1L), then this Step 5 would also include forming a new insulatingoxide layer (not shown) over the reference capacitor's conductive areas113 in the grooves 107. Since the reference capacitor's conductive areas113 may even be on the surface of the wafer A (102), and do not requireany gap, it may be suitable to simply cover the areas 113 with the sameoxide layer 104 a″ of thickness “t3” which covers the rest of the topsurface of wafer A (102).

After the oxide layers 104 a″, 114 have been grown, any protrusions onthe edges of the cavities due to sharp corner oxidation can be removedusing a mask (“Mask 5”) having a combination of the patterns on “Mask 1”and “Mask 2”, but with larger dimensions.

Step 6. FIG. 1F illustrates the result of treatments to Wafer B (150)which is then bonded to wafer A (102). First, wafer B (150) is heavilyboron doped to form a P+ silicon diaphragm layer 152. As explainedhereinabove, the manufacturing method of this invention allows the useof the less-costly diffusion doping process (e.g., diffusion using solidsource BN for 8 hours at approximately 1120° C., followed by an extrahour with 1.5 SLPM oxygen to soften the borosilicate glass so that itcan be removed by etching in BHF for about 30 minutes). Note that thelength of the time used for the diffusion doping must be controlled toachieve the desired thickness “h” of the diaphragm layer 152. Thisdiaphragm thickness “h” is a critical parameter in the design of TMCPSand is an important determinant of TMCPS characteristics andperformance. Also as explained hereinabove, an important part of thisinvention is the preparation of the diaphragm layer 152 by CMP in orderto make its diffusion doped surface smooth enough for good siliconfusion bonding (SFB). After CMP, the wafer A (102) and wafer B (150) arecleaned (e.g., by RCA cleaning), then bonded using SFB, and annealed(e.g., at 1000° C. for 1 hour).

Step 7. FIG. 1G illustrates the result of removing all of wafer B (150)except for the diaphragm 152. The P+ etch-stop technique (e.g.,dissolving the backside silicon in EDP at 115° C.) can be used tofabricate the diaphragm 152 with the designed thickness. Due to theetch-stop mechanism which greatly slows the etching rate upon reachingthe P+ layer, the diaphragm 152 thickness can be easily controlled. Thisis the final determinant of the critical dimension of the diaphragm 152thickness “h”.

Step 8. FIG. 1H illustrates the opening of a window for access to thefixed electrode contact 112 c. Using a “Mask 6”, etch the diaphragm 152away from where it covers the fixed electrode contact 112 c. This can bedone, for example, using an SF6-based plasma etch, with photo-resist asthe etching mask (“Mask 6”).

If the sensor 100 is to have an optional reference capacitor 141 (seeFIG. 1L), then this Step 8 would also include opening a window for thereference capacitor contact 113 c. If “Mask 6” is made to include thearea 113 c along with the area 112 c, then both of these areas 112 c,113 c could be patterned and etched simultaneously.

Step 9. FIG. 1I illustrates sealing the gap in the feedthrough groove106′. This is an optional step, depending on whether a differential orabsolute pressure sensor is desired. The groove gap 106′ should besealed only for an absolute pressure sensor, as discussed hereinabove.The groove gap 106′ can be sealed by depositing a thin layer 120 (e.g.,1.0 μm) of low temperature oxide (LTO) over the entire top surface ofthe sensor 100, including the areas 120 a above the diaphragm 152, thearea 120 b which covers the sides of the contact cavity 110 and thusseals the opening of the groove gap 106′, and the area 120 c whichcovers the fixed electrode contact 112 c. Note that this step must beconducted in a vacuum in order to achieve a vacuum in the sensingcapacitor cavity 108.

If there is an optional reference capacitor 141 (see FIG. 1L) present inthe sensor 100, then the reference capacitor constant 113 c which wasexposed in the previous step would also be covered by a portion (notshown) of the LTO layer 120.

Step 10. FIG. 1J illustrates opening new windows 121 through the LTOlayer 120 (using, for example, a “Mask 7” and dipping the wafer assembly100 in BHF to remove the LTO). A fixed electrode contact window 121 c isopened above the fixed electrode contact 112 c. A diaphragm window 121 ais also opened above the portion of the diaphragm 152 a above 152 aabove the sensing capacitor cavity 108, so that the flexing part of thediaphragm 152 is pure silicon of the designed thickness “h”. It may bedesirable to make the diaphragm window slightly larger than the area ofthe sensing capacitor cavity 108. Referring to FIG. 1L, it can be seenthat a diaphragm contact window 121 d must be opened above a region ofthe diaphgram 152 c where a diaphragm contact pad 132 can be placed.

If there is an optional reference capacitor 141 (see FIG. 1L) present inthe sensor 100, then a reference capacitor contact window (not shown)will need to be opened above the reference capacitor contact 113 c. If“Mask 7” is made to include the area above the reference capacitorcontact 113 c along with the areas for the other windows 121, then allof the windows could be opened simultaneously.

Step 11. FIGS. 1K and 1L show the result of metalizing to creat contactpads 130, 132, and optional 131 for better ohmic contact with the P+conductive contact areas, which are, respectively, the fixed electrodecontact 112 c, the diaphragm contact 152 c, and the optional referencecapacitor contact 113 c. The contact pads 130, 132, and optionally 131,are formed by metallization with a sputter and pattern technique, using“Mask 8”. The metal layer is, for example, approximately 7500 Å ofAl/Si/Cu.

Step 12. FIG. 1L is a partly cut away illustration of a completed SFBTMCPS sensor 100. In this final step, the wafer assembly (wafer A (102)plus wafer B (150)) is diced and then the resulting plurality of sensors100 formed on the wafer assembly can be tested and packaged.

In this manner, capacitive pressure sensors can be fabricated whichexhibit sensitivities of approximately 0.1 to 0.35 pF/psi in the linearTMCPS operating range.

SECOND PREFERRED EMBODIMENT—SIMPLIFIED MANUFACTURING METHOD

The process discussed hereinabove for the first preferred embodiment ofthe TMCPS 100 of this invention can be simplified to a three-layerprocess. Referring to the drawings, FIGS. 2A to 2F illustraterepresentative steps of a second preferred embodiment of a structure andmanufacturing process design for a touch mode capacitive pressure sensor(TMCPS) 200 based on silicon fusion bonding (SFB) technology. Theresulting sensor 200 embodiment can be seen in FIG. 2G, shown in a topview.

Throughout the following description of this embodiment of a sensor 200,a reference capacitor 241 will be included in the construction details.It should be understood that this reference capacitor 241 is an optionalpart of the overall sensor 200, and it is within the scope of thisinvention to manufacture a sensor 200 without a reference capacitor 241by eliminating those parts of the herein described manufacturing processwhich are related to the reference capacitor 241 and its variouscomponents.

The following description also assumes that the preferred embodiment isa vacuum-reference, absolute pressure sensor. It should be apparent tothose skilled in the art that this design could be changed to adifferential pressure sensor by adding process steps which would ventthe sensing cavity 208 to a second port. This could be done, forexample, by etching a hole through the backside insulation layer 204 b,wafer silicon 202 and insulator 214 into an edge of the sensing cavity208 at a periphery of the insulator 214 where the diaphragm 252 a wouldnot be touching.

In general, this second preferred embodiment of a SFB TMCPS 200 has beensimplified in a way which reduces manufacturing costs even further thanthe process described hereinabove for the first preferred embodiment100, but still maintains excellent sensor performance. Although thissecond embodiment sensor 200 does not use a floating bottom electrode,it will be seen that various techniques have been utilized to minimizeand counteract the attendant stray capacitance effects, especiallythrough use of a minimum-sized diaphragm 252 a over a proportionallymaximized size sensing cavity 208, and also through use of an optionalbut preferred reference capacitor 241 built-in to the same chip as thesensing capacitor 240. In order to simplify the construction to thissensor 200, the substrate, Wafer A (202), as a whole is used as thebottom electrode(s) for the sensing capacitor 240 and the optionalreference capacitor 241. The gap “g′” is defined by the thickness “t3”of a thermally grown oxide layer 204 a. Since there is no electrodefeedthrough required, the hermetically sealed sensing cavity 208 can beformed by silicon fusion bonding without introducing extra processesother than the CMP process for the diaphragm layer 252 as describedhereinabove for the first embodiment 100. There are preferably twocapacitors 240, 241 constructed on the sensor chip 200. One (240) isconstructed with a P+ silicon diaphragm 252 a and the substrate 202separated by a sensing cavity 208 and insulator 214, plus thesurrounding bonding area 260. This capacitor 240 is pressure sensitiveand preferably designed to operate mostly in the linear touch mode. Theother capacitor 241 is constructed with a P+ silicon diaphragm 252 d andthe substrate 202 separated by the oxide layer 204 a in the remainder261 of the diaphragm layer 252 bonding area. It is insensitive topressure and can be used as a reference capacitor 241. The completedsensor chip 200 is, for example, approximately 1.0 mm×1.5 mm×0.4 mm insize. For this exemplary size of chip 200, the diaphragm 252 a can rangein size, for example, approximately 300-400 μm in diameter.

Although the FIGS. 2A to 2G illustrate a single sensor at various stagesin the process, it should be understood that these process steps areapplied simultaneously to all the plurality of sensors, not shown, butcontained within the bounds of the same wafer assembly which containsthe illustrated sensor.

A second exemplary SFB TMCPS fabrication process, for fabricating aplurality of SFB TMCPS sensors according to the invention, includes thefollowing process steps. Although the steps are numbered for convenientreference, it is within the scope of this invention to fabricate asensor using some or all of these steps, and in any order. It shouldalso be understood that the labeling of the steps is arbitrary, for theconvenience of this explanation, so that a given “step” may actuallyinclude several discrete manufacturing processes or process stages.

Step 0. Begin with two single crystal silicon wafers: Wafer A (202)which will be used for the substrate, and Wafer B (250) which will beused to form the diaphragm layer 252. Wafer A (202) is, for example, aP-type silicon wafer, <100> orientation, with a resistivity of 2-5ohm-cm. Wafer B (250) is, for example, a P-type silicon wafer, <100>orientation, with a resistivity of 2-5 ohm-cm.

Step 1. Wafer A (202) is prepared with a thick (e.g., approximately 2.2μm) layer of oxide 204 (204 a, 204 b as can be seen in the step 2illustration of FIG. 2A) thermally grown on both flat sides. Thethickness of the backside oxide layer 204 b is not critical, but thethickness “t3” of the top oxide layer 204 a determines the initial gapof the capacitive pressure sensor. The same thickness of oxide for thebackside oxide layer 204 b can be used not only as a wet silicon etchmask, but also compensates for the stress in the top oxide layer 204 aso that the wafer can keep flat for the silicon fusion bonding process.

Step 2. FIG. 2A illustrates a sensing cavity 208 etched into the topoxide layer 204 a. The cavity can be any shape, according to the TMCPSdesign, but is typically circular, square, or rectangular. In thisexample the cavity 208 is assumed to be round, as shown in FIG. 2G. Toform the sensing cavity 208 the oxide layer 204 a is etched completelythrough, stopping at the top surface of the silicon substrate 202,thereby creating a sensing cavity depth of “g” which is approximatelythe same as the top oxide layer 204 a thickness “t3”. The oxide incavity area is etched using, for example, reactive ion etching (RIE),which can produce very vertical sidewalls after etching. The portion ofthe silicon substrate 202 which is exposed by the sensing cavity 208becomes the fixed electrode 212 for the sensing capacitor 240.

Step 3. FIG. 2B illustrates a capacitor-quality insulator (dielectric)layer 214 grown, using known techniques (e.g., wet oxidation at 950° C.)on the bottom of the sensing cavity 208. The insulating layer 214 isgrown to a thickness “t1” (e.g., 0.1 μm) according to the design of thesensor 200 and is critical to provide electrical isolation when thediaphragm 252 a touches the bottom of the cavity 208 during touch modeoperation of the TMCPS.

Step 4. FIG. 2C illustrates the bonded assembly of the two wafers, waferA (202) and wafer B (250). Before bonding, the top wafer B (250) must beprepared as in the first embodiment described hereinabove: awell-defined thickness “h” of heavily doped boron (using a diffusionprocess) creates a P+ silicon layer 252; the now-roughened surface ofthe P+ layer 252 is suitably polished using chemical-mechanicalpolishing (CMP); and then wafer B (250) is bonded to the substrate waferA (202) using the silicon fusion bonding (SFB) technique, with the P+silicon diaphragm layer 252 bonded to the insulating oxide layer 204 a.No alignment is required during the bonding. The bonding is performed ina vacuum in order to provide a vacuum reference in the resultinghermetically sealed sensing cavity 208.

Step 5. FIG. 2D illustrates the wafer assembly 200 after dissolving awaythe unwanted portion of wafer B (250). After bonding in the previousstep, the wafer assembly 200 is immersed in a dopant-dependent etchant(such as EDP, KOH and TMAH) to dissolve the pure silicon portion ofwafer B (250) until reaching the P+ silicon layer 252. Standardetch-stop techniques can be used to accurately control the dissolvingtime and thereby control the performance-critical dimension “h” which isthe resulting thickness of the diaphragm layer 252.

Step 6. FIGS. 2E and 2G illustrate the important step of patterning andetching the diaphragm layer 252. This can be done, for example, usingthe SF6-based plasma etch, with photo-resist as the etching mask. Thediaphragm layer 252 is etched completely through, stopping at theunderlying oxide layer 204 a to create a groove 255 around the cavity208 and extending out to one side of the chip 200. The groove 255defines the extent of the sensing diaphragm 252 a (with a connectingpath 252 b to a diaphragm contact area 252 c) and electrically isolatesthe areas 252 a, 252 b, and 252 c from the remainder 252 d of thediaphragm layer 252.

The dashed line marks the periphery 209 of the sensing cavity 208 hiddenunder the sensing diaphragm 252 a, so it can be seen that the area 260between the groove 255 and the sensing cavity periphery 209 becomes thebonding area for the sensing diaphragm 252 a. This diaphragm bondingarea 260 must be minimized (along with the connected areas 252 b and 252c) in order to minimize stray capacitance, but the minimum bonding areamust be determined by good design practices to provide adequate strengthfor that bend which is continually stressed by the flexing of thesensing diaphragm 252 a in response to the pressure being sensed.

Using another mask, a fixed electrode contact cavity 210 is etchedthrough an area of the top oxide layer 204 a near the edge approximatelyas shown to expose the surface of the substrate 202.

Step 7. FIGS. 2F and 2G illustrate the addition of metalized contactpads 230, 231, 232 for connecting the sensor 200 to an interfacecircuit. This can be done, for example, by forming aluminum contact padsusing a lift-off technique. Diaphragm contact pad 232 applied to thediaphragm contact area 252 c provides an electrical connection point forthe sensing diaphragm 252 a (the moving electrode of the sensingcapacitor 240). Reference capacitor contact pad 231 provides anelectrical connection point for the top electrode 252 d of the referencecapacitor 241, and substrate contact pad 230, applied to the surface ofthe substrate 202 which is exposed in the bottom of the fixed electrodecontact cavity 210, provides an electrical connection point for thebottom (fixed) electrode of both the sensing capacitor 240 and thereference capacitor 241.

Step 8. FIG. 2G is a top view illustration of a completed SFB TMCPSsensor 200. In this final step, the wafer assembly (wafer A (202) pluswafer B (250)) is diced and then the resulting plurality of sensors 200formed on the wafer assembly can be tested and packaged.

This simplified process of the second preferred embodiment utilizessingle-side processing of silicon wafers. It only requires threenon-critical masking steps and can produce very high yield.

In the preferred embodiments of manufacturing processes describedhereinabove, it should be apparent to those skilled in the art that themanufacturing processes described are not specific to any particularshape or size of sensing cavities (e.g., 108, 208). The sensing cavitiescould be square, rectangular, or circular (as in most CPS designs), orthey could even be any shape of enclosed area having a flat surface forbonding to the diaphragm. In like fashion, it should be apparent tothose skilled in the art that the sensor manufacturing processes of thisinvention can be applied to capacitive pressure sensors and otherdiaphragm-containing devices whether or not they function as a touchmode capacitive pressure sensor.

Although the invention has been illustrated and described in detail inthe drawings and foregoing description, the same is to be considered asillustrative and not restrictive in character, it being understood thatonly preferred embodiments have been shown and described, and that allchanges and modifications that come within the spirit of the inventionare desired to be protected. Undoubtedly, many other “variations” on the“themes” set forth hereinabove will occur to one having ordinary skillin the art to which the present invention most nearly pertains, and suchvariations are intended to be within the scope of the invention, asdisclosed herein.

What is claimed is:
 1. A method of fabricating silicon capacitivesensors, characterized by the steps of: providing a first silicon waferand a second silicon wafer; for each sensor, etching a groove in thefirst silicon wafer; for each sensor, etching a sensing cavity and acontact cavity, each cavity connected to an opposing end of the groovein the first silicon wafer; for each sensor, after etching the grooveand the cavities, forming a continuous and connected conductive area inthe bottoms of the groove and the cavities, in the first silicon wafer;forming a P+ conductive diaphragm layer in the second silicon wafer bymeans of diffusion doping; after the step of forming the diaphragm layerin the second silicon wafer, preparing the surface of the diaphragmlayer for bonding by polishing with a chemical-mechanical polishing(CMP) process; bonding the first silicon wafer and the second siliconwafer together using a silicon fusion bonding (SFB) technique;dissolving the second silicon wafer, except for the diaphragm layer;after the step of dissolving the second silicon wafer, for each sensor,etching open a fixed electrode contact window through the diaphragmlayer to the contact cavity; and dicing a plurality of sensors formedfrom the first and second silicon wafers.
 2. Method, according to claim1, including the steps of: providing the first silicon wafer as anN-type silicon wafer, <100> orientation, with resistivity of 5-10ohm-cm; and providing the second silicon wafer as a P-type siliconwafer, <100> orientation, with resistivity of 2-5 ohm-cm.
 3. Method,according to claim 1, including the steps of: for each sensor, afterforming a conductive area in the bottom of the sensing cavity, formingan oxide layer over the conductive area in the bottom of the sensingcavity, in the first silicon wafer; and after forming a conductive areain the bottom of the groove which connects to the sensing cavityconductive area, forming an oxide layer over the conductive area in thebottom of the groove (106) and extending into the sensing cavity, in thefirst silicon wafer.
 4. Method, according to claim 1, including thesteps of: sealing the grooves by depositing a layer of LTO; and maskingand etching the LTO layer to open windows through the LTO layerincluding a diaphragm window, a fixed electrode contact window, adiaphragm contact window, and a window above a reference capacitorcontact, if present.
 5. Method, according to claim 1, including the stepof: for each sensing capacitor in each sensor, fabricating an associatedreference capacitor with a reference capacitor bottom electrode, areference capacitor bottom electrode contact, a reference capacitorfeedthrough which electrically connects the reference capacitor bottomelectrode to the reference capacitor bottom electrode contact, areference capacitor contact pad, a dielectric oxide layer, and a topelectrode which is the diaphragm layer.
 6. Method, according to claim 1,for each sensor, after the step of etching open a window through thediaphragm layer to the fixed electrode contact cavity, further includingthe steps of: depositing metallization on the fixed electrode contact toform a sensing capacitor fixed electrode contact pad; and depositingmetallization on the diaphragm layer to form a diaphragm contact pad. 7.Method, according to claim 1, including the step of: during the step ofetching the cavities, over-etch to create a step around the periphery ofthe cavities.
 8. Method, according to claim 1, including the step of:during the step of etching the cavities, round off edges of thecavities.
 9. Method, according to claim 1, wherein the step of formingthe conductive area for each sensor further includes the steps of:applying and patterning a masking layer; and heavily diffusing boron(+).
 10. Method, according to claim 1, further including the step of:prior to silicon fusion bonding the wafers, preparing the wafers forsilicon fusion bonding by RCA cleaning.
 11. Method, according to claim1, including the step of dissolving the second silicon wafer by:dissolving in EDP.
 12. A silicon capacitive sensor including a firstsilicon wafer and a second silicon wafer, characterized by: a grooveetched in the first silicon wafer; a sensing cavity and a contact cavityetched in the first silicon wafer with each cavity connected to anopposing end of the groove; a continuous and connected conductive areain the bottoms of the groove and the cavities, in the first siliconwafer; a P+ conductive diaphragm layer formed in the second siliconwafer; the first and second wafers being bonded together, with thesecond silicon wafer being dissolved except for the diaphragm layer; anda window through the diaphragm layer to the contact cavity.
 13. Asilicon capacitive sensor, according to claim 12, characterized in that:the first silicon wafer is an N-type silicon wafer with resistivity of5-10 ohm-cm; and the second silicon wafer is a P-type silicon wafer withresistivity of 2-5 ohm-cm.
 14. A silicon capacitive sensor, according toclaim 12, characterized in that: an oxide layer is over the conductivearea in the bottom of the sensing cavity; and an oxide layer is over theconductive area in the bottom of the groove and extends into the sensingcavity.
 15. A silicon capacitive sensor, according to claim 12,characterized in that: the grooves are sealed by a deposited layer ofLTO; and windows pass through the LTO layer to form a diaphragm window,a fixed electrode contact window, a diaphragm contact window, and awindow above a reference capacitor contact.
 16. A silicon capacitivesensor, according to claim 12, further characterized by: a sensingcapacitor; and an associated reference capacitor with a referencecapacitor bottom electrode, a reference capacitor bottom electrodecontact, a reference capacitor feedthrough which electrically connectsthe reference capacitor bottom electrode to the reference capacitorbottom electrode contact, a reference capacitor contact pad, adielectric oxide layer, and a top electrode being the diaphragm layer.17. A silicon capacitive sensor, according to claim 12, characterized inthat: deposited metallization on the fixed electrode contact forms asensing capacitor fixed electrode contact pad; and depositedmetallization on the diaphragm layer forms a diaphragm contact pad. 18.A method for forming an electrical feedthrough to a conductor in acavity formed in a first silicon wafer, wherein the first silicon waferis bonded to a second silicon wafer, characterized by the steps of:etching a groove in the first silicon wafer; etching the cavity and acontact cavity, each cavity connected to an opposing end of the groovein the first silicon wafer; forming a continuous and connectedconductive area in the bottoms of the groove and the cavities, in thefirst silicon wafer; bonding the first and second wafers together usingsilicon fusion bonding (SFB); etching a window through the second waferto the contact cavity on the first silicon wafer; forming an oxide layerover the conductive area in the bottom of the sensing cavity, in thefirst silicon wafer; and forming an oxide layer over the conductive areain the bottom of the groove and extending into the cavity, in the firstsilicon wafer.
 19. A method for forming an electrical feedthrough to aconductor in a cavity formed in a first silicon wafer, wherein the firstsilicon wafer is bonded to a second silicon wafer, characterized by thesteps of: etching a groove in the first silicon wafer; etching thecavity and a contact cavity, each cavity connected to an opposing end ofthe groove in the first silicon wafer; forming a continuous andconnected conductive area in the bottoms of the groove and the cavities,in the first silicon wafer; bonding the first and second wafers togetherusing silicon fusion bonding (SFB); etching a window through the secondwafer to the contact cavity on the first silicon wafer sealing thegroove by depositing LTO; and opening a window above a contact portionof the conductive area, by etching the LTO.